Deep submicron CMOS technologies are today widely used in mixed-signal front-end systems. They provide the required integration density and are very promising in terms of radiation hardness. As far as analog performances are concerned, the trend toward device scaling brings along the need of understanding the noise properties of transistors with channel length of a few tenth of a micron. In the framework of this research program, an accurate model for the noise behavior of deep submicron CMOS devices has been developed, paying particular attention to short-channel effects and to parasitic contributions from gate and substrate resistors. The model has been assessed through an extensive comparison with experimental results. Devices belonging to CMOS and BiCMOS processes from 350 nm to 90 nm of minimum channel length were characterized. Noise measurements have been carried out by means of a purposely developed wide band transimpedance amplifier. High density front-end systems are designed according to low-power criteria. It is therefore most important to predict the noise performance of the devices at small overdrive voltages. The study of the experimental noise data relevant to P and N-channel MOSFETs working in this operating region may provide effective tools to the design of low-noise, low-power analog blocks. CMOS transistors belonging to the mentioned technologies have been exposed to gamma-rays from a 60-Co source and changes in static, signal and noise parameters have been monitored.